Blog Archives - Protostar Labs

Mitigating radiation effects in FPGAs

The TMR VHDL Library makes it easy to add Triple Modular Redundancy to your FPGA designs. By triplicating critical logic and using a voter circuit, it protects against faults from Single Event Effects. With a simple USE_TMR switch, you can turn redundancy on or off, speeding up development while ensuring your IP can be industrial- or space-grade ready.

Protostar Labs signs ESA contract for chromosphere monitoring instrument

Protostar Labs is happy to announce the signing of a new contract with the European Space Agency for the development of CROMIS, the ChROmosphere Monitoring InStrument. Funded under ESA’s Call for Proposals for Croatian entities, this project, beginning on September 15, 2025, marks a major milestone for Croatia in space science and astrophysics.

Shortwave infrared (SWIR) imaging Part 2: Public safety and defense

Discover how SWIR imaging revolutionizes public safety and defense, from penetrating smoke in fire rescue operations to detecting camouflaged threats and hidden mines, transforming visibility and efficiency in critical scenarios.

Shortwave infrared (SWIR) in machine vision imaging and other technologies – Part 1

This blog series explores the fundamentals and diverse applications of Short-Wave Infrared (SWIR) imaging, highlighting its critical role in industries such as agriculture, food production, pharmaceuticals, electronics, and space exploration, where it enables advanced material analysis, quality control, and remote sensing by leveraging unique spectral characteristics invisible to the human eye.

Attendance of the International Astronautical Congress 20204 in Milan

Sharing our experiences at the IAC 2024 Milan

Exhibition at DEFCROS Public Safety & Defense Expo

A showcase of our latest technologies at the first international DEFCROS Public & Safety Expo in Osijek.

Exploring VDMA and Implementing Loop Testing on the PYNQ Z2 FPGA Platform

In our previous blog post, we explored the development and implementation of a Sobel filter IP core on the PYNQ Z2 FPGA. There we explained how to design the filter in Vitis HLS, export and integrate the IP (Intellectual Property) core into Vivado, and finally control the Sobel Filter using Direct Access Memory (DMA) in the PYNQ environment. In this post, we will be using a different approach called Video Direct Memory Access (VDMA). It is similar to the DMA, but designed for video applications.

Creating and Implementing a Sobel Filter IP core on the PYNQ Z2 FPGA platform

This blog post explores the development and implementation of Sobel filter IP core on the PYNQ Z2 FPGA. You will learn to design the filter in Vitis HLS, how to export and integrate the sole IP core in Vivado and finally control the Sobel (using DMA) in PYNQ Jupyter Notebook.